Abstract

Photonic reservoir computing has evolved into a viable contender for the next generation of analog computing platforms as industry looks beyond standard transistor-based computing architectures. Integrated photonic reservoir computing, particularly on the silicon-on-insulator platform, presents a CMOS-compatible, wide bandwidth, parallel platform for implementation of optical reservoirs. A number of demonstrations of the applicability of this platform for processing optical telecommunication signals have been made in the recent past. In this work, we take it a stage further by performing an architectural search for designs that yield the best performance while maintaining power efficiency. We present numerical simulations for an optical circuit model of a 16-node integrated photonic reservoir with the input signal injected in combinations of 2, 4, and 8 nodes, or into all 16 nodes. The resulting error performance on the temporal XOR task for these multiple input cases is compared with that of the typical case of input to a single node. We additionally introduce for the first time in our simulations a realistic model of a photodetector. Based on this, we carry out a full power-level exploration for each of the above input strategies. Multiple-input reservoirs achieve better performance and power efficiency than single-input reservoirs. For the same input power level, multiple-input reservoirs yield lower error rates. The best multiple-input reservoir designs can achieve the error rates of single-input ones with at least two orders of magnitude less total input power. These results can be generally attributed to the increase in richness of the reservoir dynamics and the fact that signals stay longer within the reservoir. If we account for all loss and noise contributions, the minimum input power for error-free performance for the optimal design is found to be in the ≈1 mW range.

Related Research Topics

• Photonic Reservoir Computing

Related Projects

• H2020: Phresco (Photonic Reservoir Computing)